1. Field of the Invention
The present invention relates to a semiconductor device in which an active element such as a CMOS-FET is mounted on a semiconductor substrate, and a method of manufacturing the device.
2. Description of the Related Art
In this type of semiconductor device, it is supposed that a gate wire width is reduced in a channel length direction (L direction) to narrow a gap between channels in order to enhance a driving force of a MOS-FET using a conventional technique. However, it is very difficult to set the gate wire width to 10 nm or less by micro processing. Even when increasing a concentration of impurities to be implanted in a P-type or N-type source•drain region, the enhancement of the driving force of the MOS-FET can be expected. However, there is trade-off between the impurity concentration and frequency of generation of crystal defects, and it is technically difficult to enhance the force by the increasing of the concentration.
Moreover, in Jpn. Pat. Appln. KOKAI Publication No. 2003-60076, there is described a semiconductor device including: a nitride film coating an n-channel MOSFET and having an intrinsic tensile stress; and a nitride film coating a p-channel MOSFET and having an intrinsic compressive stress.
In Jpn. Pat. No. 3441259, there is described a semiconductor device comprising: a semiconductor substrate having a first trench filled with a first material; a semiconductor layer formed on the semiconductor substrate and having a second trench filled with a second material; and a semiconductor element formed on the semiconductor layer. The first material has a thermal expansion coefficient which is different from that of the semiconductor substrate, and a thermal expansion coefficient difference between the second material and the semiconductor layer is smaller than that between the first material and the semiconductor substrate.